1. Field of the Invention
The present invention relates to a fabrication method of a semiconductor memory device, and more particularly, to an improved fabrication method for a memory cell of a semiconductor DRAM device which has a capacitor over bit line ("COB") structure.
2. Description of the Prior Art
Generally, because of increasingly high integration for a semiconductor memory device, many kinds of memory cell arrays and structures to be compatible with high integration have been suggested.
As shown in FIGS. 1A and 1B, a conventional art memory cell array is represented as having a capacitor under bit line (CUB) structure in which a capacitor 13 is formed on a rectangular active array 12 that is formed on a semiconductor substrate 11 and then a bit line 14 is formed thereon. Reference numeral 15 represents a gate line.
However, the memory cell having the above CUB structure has a limited capacitor area because the capacitor is located under the bit line. Therefore, the capacitor height must be increased so as to secure a capacitance level corresponding to that of the high integrated semiconductor memory device of the conventional art where the area for the capacitor has sharply decreased. Having a decreased capacitor area increases a bit line contact hole aspect ratio. Consequently, there are technical difficulties when filling a contact hole and forming a line pattern for a bit line. Accordingly, a semiconductor memory device for a 16M DRAM type, 64M DRAM type, or higher DRAM type requires a new cell array type structure.
FIGS. 2A and 2B show a semiconductor memory device having a COB structure disclosed in U.S. Pat. No. 5,140,389 which is hereby incorporated by reference. As shown in these drawings, the COB structure shows a bit line 23 formed before a capacitor 24 so as to secure a region on the bit line 23 as a region for the capacitor 24. Thus, a capacitance level is increased, and a bit line contact hole aspect ratio is decreased. As a result, filling a contact hole and forming the bit line 23 is simplified.
In the above COB structure, the capacitor 24 is formed on the bit line 23, and an active region 22 is designed to have a diagonal shape so that the active region 22 crosses with the bit line 23 and a word line 25. Since the active region 22 is diagonal in shape, there are more corners than the conventional active region 12 of FIG. 1A which causes serious shrinkage and distortion when performing a process involving photolithography. As a result, forming the active region pattern becomes difficult. Moreover, the diagonal active region 22 has a lower packing density in a predetermined area than the rectangular active region 12 of FIG. 1A; thereby causing a disadvantage in high integration. Accordingly, ultra high integrated 256M DRAM type devices as above require a new cell array type structure. A representative example, as shown in FIG. 3, shows a cell array structure using a T-shaped active region 32 that increases packing density to solve the low packing density of the diagonally shaped active regions. In FIG. 3, reference numerals 33 and 35 represent a bit line and a gate line, respectively.
However, since the T-shaped active region 32 also has more corners than the rectangular active region 12 of FIG. 1A, serious shrinkage or distortion occurs in performing a photolithography process, thereby causing many problems in forming an active region. To solve the above problems, as shown in FIG. 4, a new cell array structure having an oblique active region 42 is suggested. In FIG. 4, reference numerals 43 and 45 represent a bit line and a gate line, respectively.
FIGS. 5A through 5E are longitudinal cross-sectional views, taken along the line 5--5 in FIG. 4, showing a fabrication method for a semiconductor memory device having the conventional COB structure.
First, an oblique active region 42, as shown in FIG. 4, is formed on a semiconductor substrate 41 by a photo-etching method. Then, as shown in FIG. 5a, to electrically cut off single devices, a device isolation process is carried out, forming a field oxide region 50 and a silicon thermal oxide film which serves as a gate insulating film 51, using a thermal oxidation method on the semiconductor substrate 41. The silicon thermal oxide film is heated in an electric furnace at a H.sub.2 /0.sub.2 atmosphere to obtain a thickness of about 80 .ANG. which forms the gate insulating film 51. Then, on the gate insulating film 51, a polycrystalline silicon or an amorphous silicon film, which serves as a gate electrode 45, is formed to have a thickness of about 2000 .ANG. by a low-pressure chemical vapor deposition ("LPCVD") method. Initially, the polycrystalline silicon or amorphous silicon film is undoped which becomes doped by ion implantation. The ion implantation can be performed while the polycrystalline film is being deposited. Then a silicon oxide film is deposited to have a thickness of about 1500 .ANG. on the silicon film, which serves as the gate electrode 45, by the LPCVD method. Then, using the photo etching method, the silicon oxide film, the polysilicon film, and the silicon thermal oxide film are sequentially etched to form a polycrystalline gate pattern which includes the gate insulating film 51, the gate electrode 45, and the silicon oxide film 53, as shown in FIG. 5A. Next, on the entire surface of the above structure, an undoped oxide film is deposited and the oxide film is anisotropically etched using the reactive ion etching ("RIE") method to form a sidewall spacer 55 at a side wall of the gate electrode 45. Then, an oxide film which serves as an insulating film 57 is deposited to a thickness of about5000 .ANG. on the entire resultant surface. Here, a 03 tetra-ethyl-orthosilicate ("03 TEOS") or a boron phosphorus silicate glass ("BPSG") which can be easily planarized (i.e., flattened) is used as a material for the insulating film 57.
As shown in FIG. 5B, a photoresist film 59 is coated on the insulating film 57 to form a photoresist film pattern for forming a contact hole. The contact hole serves as a path for electrically connecting the active region 42 and a bit line 43 to be formed later.
Then, as shown in FIG. 5C, an exposed portion of the insulating film 57 is etched to form the contact hole 61, using the patterned photoresist film 59 as a mask, until the surface of the active region 42 on the semiconductor substrate 41 is exposed. Then the photoresist film 59 is stripped off. Portions of the insulating film 57 protect the lateral spacer 55 and the insulating film 53 from being etched away when forming the contact hole 61. Here, the etching is carried out using the RIE method with a plasma of CHF.sub.3 or CF.sub.4 gas.
Next, as shown in FIG. 5D, sidewalls 63 are formed at lateral walls of the contact hole 61, and as shown in FIG. 5E, a polycrystalline film, which serves as the bit line 43, is deposited using the LPCVD method on the entire resultant surface to have a thickness of about 2000 .ANG.. Then, a metal silicide is formed to have a thickness of about 1000 .ANG. on the polysilicon film using the chemical vapor deposition ("CVD") method, and then the photoresist film (not illustrated) is coated on the metal silicide film, to form the photoresist film pattern for forming the bit line 43. Next, a bit line pattern is formed by sequentially etching the metal silicide film and the polysilicon film which are exposed using the RIE method with the patterned photoresist film acting as a mask. Then the photoresist film pattern is removed. A subsequent processes complete the formation of the semiconductor memory device by forming a capacitor (not illustrated) on the bit line 43. These subsequent processes are identical to the conventional fabrication method for a semiconductor memory device; therefore, the description thereof will be omitted.
However, in the semiconductor DRAM device having the above conventional oblique active region and the COB structure, the oblique active region can reduce serious shrinkage or distortion of the active region pattern, and the COB structure can reduce an aspect ratio of the contact hole for contacting the bit line. However, with high integration difficulty for fabricating semiconductor DRAM devices, development of a 1G type DRAM device is under progress. Accordingly, for a 1G type DRAM device, a design rule of below 0.2 .mu.m is required. Consequently, it is difficult to design a cell block when the size of the contact hole becomes critical in size resulting in a difficult process. Because of increasingly high integration, complicated process steps are required that increase production costs. Therefore, process simplification is essentially required.